Civil and Environmental Engineering
Reconfigurable Systems for Space
(C-ITS)
The processing speed, cost and flexibility requirements of future satellite-based applications cannot be satisfied with conventional radiation-hardened processors or custom integrated circuits. SRAM-based Field Programmable Gate Arrays (FPGAs) provide an opportunity for meeting these requirements with off-the-shelf hardware. The main challenge of using FPGAs for space applications is mitigating the effects of radiation-induced Single Event Upsets (SEUs).
The aim of the two projects supported in part by the Australian Research Council’s Linkage (LP140100328) and Discovery (DP150103866) Projects funding schemes is to develop key technology to enable off-theshelf hardware to be customized for this use without compromising reliability. The projects will develop the design methods needed to implement a given set of satellite applications on a processing platform composed of application-specific soft processors and accelerator circuits hosted on conventional reconfigurable logic devices. Crucially, the solution architecture will be sufficiently hardened against radiation-induced errors to meet reliability targets while satisfying performance and energy use constraints. During the course of these projects, these techniques will be demonstrated and tested in-orbit on the RUSH payload for the  which is a part of the international QB50 CubeSat program funded by the European Union Framework project.
During 2015 a part-time research was identified and appointed in late 2015 on the LP140100328 project and a full-time researcher was identified and will take up his position early in 2016 on the DP150103866 project. Research work concentrated on the design and reliability aspects of the reconfiguration control network and its performance evaluation. In tandem with this, current research is looking at fault-tolerant reconfiguration network controller design. Research was also undertaken to reduce the overheads associated with using Dynamic Partial Reconfiguration (DPR) to overcome configuration memory errors in TMR systems.
In addition to these, considerable amount of activity has focused on the QB50 RUSH payload design and experiment. The payload board was designed and built while the firmware was developed. The payload supports two configurations, one looking at the efficacy of recovering from radiation-induced SEUs using our proposed modular recovery approach and another which uses the traditional scrubbing approach. The payload has been successfully integrated into the  bus and has passed the thermal and vacuum environmental tests with flying colours. These will be followed by vibration tests in 2016 and subsequent shipment of the CubeSat for launch to Europe around June 2016.
School
°ä´Ç²Ô³Ù²¹³¦³ÙÌýDr Ediz CetinÌý²¹²Ô»å/´Ç°ùÌýA/Prof Oliver Diessel for further information and research opportunities.